This application claims the priority benefit of Taiwan application serial no. 90132737, filed Dec. 28, 2001.
1. Field of Invention
The present invention relates to a wafer level package. More particularly, the present invention relates to a wafer level package capable of removing the effects due to a difference in thermal expansion coefficient between a chip and corresponding circuit board within the wafer level package.
2. Description of Related Art
In this information proliferation age, the electronic equipment has become an indispensable tool in our daily life. Integrated circuit devices are incorporated into many types of products for commercial, educational, recreational and other uses. Following the rapid advance in electronic manufacturing technologies and the integration of powerful functions, all kinds of personalized products have been developed. In general, the development of miniaturized electronic products is the major trend. Thus, in the semiconductor industry, the trend is also towards the production of high-density packages. To produce high-density packages, chip scale package techniques are often employed. With such techniques, the ultimate size of a package differs not too much from the size of the enclosed chip. There are several production methods for forming a chip scale package, in which the most common method is the so-called wafer level packaging. As the name implies, the chip is fully packaged when the wafer is diced up into separate chips.
To produce a wafer level package, a wafer comprising a plurality of chips with scribe lines cutting across the area between neighboring chips is provided. Thereafter, a redistribution layer is formed over the active surface of the wafer. Bumps are formed at various locations over the redistribution layer. Finally, the wafer is cut up into individual chips. The cutting process also cuts up the redistribution layer structures between neighboring chips to form independent flip chip packages such as the one shown in FIG. 1. FIG. 1 is a schematic cross-sectional side view of a conventional wafer level flip-chip package structure. As shown in FIG. 1, each flip-chip package 100 includes a silicon chip 110, a redistribution layer structure 120 and a plurality of bumps 130. The silicon chip 110 has a multiple of bonding pads 114 on the active surface 112 of the chip 110. The redistribution layer structure 120 is a layer formed over the active surface 112 of the chip 110. The redistribution layer 120 comprises an insulation layer 122 and a plurality of metallic circuit lines 124. The metallic circuit lines 124 criss-cross each other within the insulation layer 122 and connect electrically with the bonding pads 114. The bumps 130 are electrically connected to various metallic lines 124 at various locations above the redistribution circuit layer 120.
In general, a flip-chip package 100 is mounted to a substrate board 140. The substrate board 140 has a plurality of bump pads 144 and a plurality of solder ball pads 148. The bump pads 144 are located on the upper surface 142 of the substrate board 140 while the solder ball pads 148 are located on the lower surface 146 of the substrate board 140. A solder reflow process may be conducted by sprinkling a reflux agent (not shown) over the substrate board 140 and heating to join the bumps 130 on the flip-chip package 100 with the bump pads 144 on the substrate board 140.
Thereafter, filler material 150 is deposited into the space between the flip-chip package 100 and the substrate board 140 so that the bumps 130 are entirely enclosed. A plurality of solder balls 160 is mounted to the solder ball pads 148 on the substrate board 140. Through the solder balls 160, the substrate board 140 may connect electrically with a printed circuit board (not shown).
Since the silicon chip 110 and the substrate board 140 are made from different materials and hence each has different thermal expansion coefficient, filler material 150 must be inserted into the space between the chip 110 and the substrate 140 to prevent thermal stress resulting from heat cycles. Repeated thermal stress may lead to the breakup of bumps 130. However, because the gap between the chip 110 and the substrate 140 is very small, the filler material 150 is actually passed into the space slowly through capillary effect. Hence, the fill-up process is not only time-consuming and costly, but the space between the flip-chip package 100 and the substrate 140 is very often not completely filled. Furthermore, one end of the bumps 130 joins up with the redistribution circuit layer 120 over the chip 110 while the opposite end of the bump 130 joins up with the bump pads 144 on the substrate 140. Thus, thermal stress between the chip 110 and the substrate 140 often leads to the production of a shear force that may break up the bump 130 in a lateral direction.
Accordingly, one object of the present invention is to provide a wafer level packaging structure and fabricating process capable of reducing production cost.
A second object of this invention is to provide a wafer level package structure and fabricating process capable of minimizing shear stress due to a difference in thermal expansion coefficient between the wafer and a substrate board.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a chip structure. The chip structure includes a wafer, an insulation layer, conductive paste, a plurality of ball pads, a solder mask and a plurality of solder balls. The chip has an active surface and the insulation layer is applied over the active surface of the chip.
The insulation layer has a plurality of open windows. The conductive paste fills the open windows. The ball pads are formed over the insulation layer in electrical contact with the conductive paste. The solder mask covers the insulation layer but exposes the ball pads. The solder balls are mounted to the ball pads.
According to one preferred embodiment of this invention, a redistribution circuit layer may form in the space between the insulation layer and the chip. The redistribution circuit layer includes an insulation layer and a plurality of metallic circuit lines. The metallic circuit lines crisscross each other inside the insulation layer. The metallic circuit lines are electrically connected to the conductive paste and the chip. In addition, a bump may be inserted into the open windows so that the conductive paste is in electrical contact with the bump.
This invention also provides a method of forming a wafer level package. First, a silicon wafer is provided. The wafer has an active surface. An insulation layer is formed over the active surface of the wafer. A plurality of open windows is formed in the insulation layer. Conductive paste is passed into the open windows. A metallic layer is formed over the insulation layer. The metallic layer is patterned to form a plurality of ball pads that connect electrically with the conductive paste. A solder mask that exposes the ball pads is formed over the insulation layer. Solder balls are implanted on the exposed ball pads. Finally, the wafer together with the insulation layer is diced up to form independent chip packages.
One preferred embodiment of this invention, before forming the insulation layer over the active surface of the wafer, further includes forming a redistribution circuit layer over the active surface of the wafer. The insulation layer is next formed the redistribution circuit layer. The wafer further includes a plurality of bumps on the active surface positioned inside the opening of the insulation layer.
In the wafer level package structure, since the bumps are surrounded by conductive paste, the bump and corresponding solder ball are electrically connected together through the conductive paste. Because the conductive paste has good extensibility, shear stress on the bumps due to thermal stress between the wafer and a printed circuit board is minimized. The diced up package occupies a relatively small space. In fact, the sectional area of the package is almost identical to the chip. Furthermore, all bumps are formed inside the open windows of the insulation layer. Hence, overall thickness of the individual package is reduced. In addition, according to the wafer level package manufacturing process of this invention, the chip and the substrate are fabricated separately and subsequently integrated together. This arrangement lowers the production cost of each package considerably.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.